Semiconductor device manufacturing method including forming a metal silicide layer on an indium-containing layer

ABSTRACT

The present invention provides a semiconductor device manufacturing method of a semiconductor device having a contact plug, in which a contact hole formed by a surface portion of a high-concentration N-type diffusion layer formed on a semiconductor silicon substrate surface and an interlayer insulating film is implanted with indium ions at an energy ranging from 30 to 120 keV and an implantation amount ranging from 1.0×10 13 /cm 2  to 5.0×10 14 /cm 2  to grow an indium-containing layer on the surface portion of the high-concentration N-type diffusion layer at the bottom of the contact hole.

RELATED APPLICATIONS

This application is a Divisional of U.S. application Ser. No.11/417,044, filed May 4, 2006, claiming priority of Japanese ApplicationNo. 2005-136726, filed May 9, 2005, the entire contents of each of whichare hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device manufacturingmethod, and particularly to a method of manufacturing a semiconductordevice having a contact plug.

2. Related Art

In a semiconductor device, a semiconductor silicon substrate and anupper wiring layer are generally connected by use of a contact plug.

Here, a conventional method of manufacturing a semiconductor device isdescribed with reference to FIGS. 1A through 1E.

As shown in FIG. 1A, an interlayer insulating film 2 made of SiO₂ or thelike is formed on a semiconductor substrate 1.

Then, a photoresist layer (not shown) is formed at a given position onthe aforementioned interlayer insulating film 2, and this photoresistlayer is used as a mask in a well-known dry etching process to form acontact hole 3 shown in FIG. 1B.

Next, as shown in FIG. 1C, a sputtering process is performed to form atitanium layer 4 on the surface of the contact hole 3. Then, annealingtreatment is performed in an atmosphere of N₂ gas thereby to make thetitanium layer 4 become a barrier layer 6 of TiN as illustrated in FIG.1D. At this point, a metal silicide layer 5 of TiSi₂ is formed on thesemiconductor silicon substrate 1 under the bottom of the contact hole3.

Then, provided on the aforementioned contact hole 3 is a conductinglayer comprised of tungsten, polysilicon containing impurities or thelike to form a contact plug 7 as shown in FIG. 1E.

The resistance of the thus formed contact plug is preferably lower so asto reduce power consumption of the semiconductor device. For the purposeof reducing the resistance of the contact plug and the like, there isknown a method of forming a TiSi₂ layer at the bottom of theaforementioned contact hole.

Meanwhile, there is also known a method of manufacturing an insulatedgate field effect transistor, as shown in FIGS. 2A and 2B, by implantingthe whole surface of the N-type diffusion layer of the semiconductorsilicon substrate with indium ions.

This method is explained below:

First, as shown in FIG. 2A, a device separation insulating region 13 andan insulating film 14 are formed on the semiconductor silicon substrate.Then, phosphorus ions and boron ions are implanted into thesemiconductor silicon substrate and thereby, a P-type well 8 and anN-type well 9 are formed in the semiconductor silicon substrate.

This is followed by selectively implanting boron ions into the P-typewell 8 and phosphorus ions into the N-type well 9. Then, a P-typehigh-concentration well layer 10 and an N-type high-concentration welllayer 11 are formed on the P-type well 8 and the N-type well 9,respectively.

After that, indium ions are implanted into the whole surface of theP-type well 8 and the N-type well 9 and thereby, an indium-containinglayer 12 is formed on the semiconductor silicon substrate.

Further, as shown in FIG. 2B, arsenic ions are selectively implantedinto the P-type high-concentration well layer 10 with a gate electrodestructure 20, which is provided on the semiconductor silicon substrate,used as an implantation blocking mask, and thereby high-concentrationN-type diffusion layers 15 and 16 are formed.

Likewise, BF₂ ions are selectively implanted into the N-typehigh-concentration well layer 11 and thereby high-concentration P-typediffusion layers 17 and 18 are formed.

Here, the high-concentration N-type diffusion layers 15 and 16 and thehigh-concentration P-type diffusion layers 17 and 18 correspond to asource/drain structure of the insulated gate field effect transistor.

The just-described method of manufacturing a semiconductor device havingan indium-containing layer, is proposed in Japanese Patent ApplicationPublication No. 2002-368212.

BRIEF SUMMARY OF THE INVENTION

However, with downsizing and high integration of semiconductor devicesin recent years, as the diameter of the contact hole is smaller, onlythe TiSi₂ layer grown at the bottom of the contact hole is not enough toprevent increase in the resistance value of the contact plug.

Further, the aforementioned method of implanting indium ions into thewhole surface of the N-type high-concentration diffusion layer presentsa problem that the indium ions, which are larger in atom radius thansilicon, may cause silicon crystal defects in the semiconductor siliconsubstrate. Accordingly, it is required to set the implantation amount ofindium ions at 5×10¹¹/cm² or less.

The present invention has an object to provide a semiconductor devicemanufacturing method of a semiconductor device having a contact plug ofexcellent resistance.

As a result of keen examination to overcome the aforementioned problem,the inventor of the present invention have found that a semiconductordevice having a contact plug of excellent resistance can be achieved bythe semiconductor device manufacturing method comprising: forming acontact hole which reaches a high-concentration N-type diffusion layerprovided on a surface of the semiconductor silicon substrate; andimplanting indium ions of opposite conductivity type to the N-type viathe contact hole, in which an implantation amount of the indium ionsfalls within a range from 1.0×10¹³/cm² to 5.0×10¹⁴/cm², and completedthe present invention successfully.

Specifically, the present invention provides:

[1] a semiconductor device manufacturing method comprising the steps of:

(1) forming a high-concentration N-type diffusion layer on a surface ofa semiconductor silicon substrate;

(2) forming an interlayer insulating film on the semiconductor siliconsubstrate with the high-concentration N-type diffusion layer;

(3) etching a predetermined position of the interlayer insulating filmto form a contact hole reaching the high-concentration N-type diffusionlayer;

(4) implanting a surface portion of the high-concentration N-typediffusion layer with indium ions at an energy ranging from 30 to 120 keVand an implantation amount ranging from 1.0×10¹³/cm² to 5.0×10¹⁴/cm² viathe contact hole to grow an indium-containing layer at a bottom of thecontact hole;

(5) forming a metal silicide layer on the indium-containing layer formedat the bottom of the contact hole;

(6) forming a barrier layer on an upper surface of the interlayerinsulating film and an inner surface of the contact hole other than thebottom of the contact hole; and

(7) forming a contact plug in the contact hole.

The present invention further provides:

[2] a semiconductor device manufacturing method according to theabove-mentioned item [1], in which the metal silicide layer is of atleast one selected from the group consisting of TiSi₂, CoSi₂, TaSi₂,PtSi₂ and NiSi₂.

The present invention further provides:

[3] a semiconductor device manufacturing method according to theabove-mentioned item [1] or [2], in which an acceleration energy forimplantation of the indium ions ranges from 40 to 100 keV.

The present invention further provides:

[4] a semiconductor device manufacturing method according to any one ofthe above-mentioned items [1] to [3], in which the implantation amountranges from 4.0×10¹³/cm² to 1.0×10¹⁴/cm².

The present invention further provides:

[5] a semiconductor device manufactured by the semiconductor devicemanufacturing method according to any one of the above-mentioned items[1] to [4].

The present invention further provides:

[6] a semiconductor device comprising:

a semiconductor silicon substrate;

a high-concentration N-type diffusion layer provided on a surface ofsaid semiconductor silicon substrate;

an indium-containing layer provided in said high-concentration N-typediffusion layer;

an interlayer insulating film provided at a predetermined position onsaid semiconductor silicon substrate;

a barrier layer provided in contact with an inner surface of a contacthole defined by the surface of said semiconductor silicon substrate andsaid interlayer insulating film and with said interlayer insulatingfilm;

a contact plug provided in contact with said barrier layer; and

a metal silicide layer provided at a boundary region between saidindium-containing layer and said barrier layer,

in which indium concentration of said indium-containing layer rangesfrom 5.0×10¹⁸/cm³ to 5.0×10¹⁹/cm³.

The present invention further provides:

[7] a semiconductor device according to the above-mentioned item [5] or[6], comprising an N channel insulated gate field effect transistorstructure.

The semiconductor device manufacturing method of the present inventionmakes it possible to provide a semiconductor device having a contactplug of excellent resistance.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects and features of the invention will appearmore fully hereinafter from a consideration of the following descriptiontaken in connection with the accompanying drawing wherein one example isillustrated by way of example, in which;

FIGS. 1A to 1E are cross sectional views each partially illustratingsubstantial parts for explaining a method of manufacturing a contactplug;

FIGS. 2A and 2B are cross sectional views each partially illustratingsubstantial parts for explaining conventional method of manufacturing aninsulated gate field effect transistor;

FIG. 3 is a cross sectional view partially illustrating substantialparts of a semiconductor device obtained by the present invention;

FIG. 4 is a cross sectional view partially illustrating substantialparts of a semiconductor silicon substrate for explaining themanufacturing method of the present invention;

FIG. 5 is a partial cross sectional view illustrating an interlayerinsulating film formed on the semiconductor silicon substrate forexplaining the manufacturing method of the present invention;

FIG. 6 is a partial cross sectional view illustrating a contact holeformed in the interlayer insulating film for explaining themanufacturing method of the present invention;

FIG. 7 is a partial cross sectional view illustrating anindium-containing layer formed on the semiconductor silicon substratefor explaining the manufacturing method of the present invention;

FIG. 8 is a partial cross sectional view illustrating a barrier layerformed on the contact hole for explaining the manufacturing method ofthe present invention;

FIG. 9 is a partial cross sectional view illustrating a cobalt layerformed on the contact hole for explaining a modified example of thepresent invention;

FIG. 10 is a partial cross sectional view illustrating a metal silicidelayer formed for explaining the modified example of the presentinvention;

FIG. 11 is a partial cross sectional view illustrating the contact holewith the cobalt layer removed from for explaining the modified exampleof the present invention; and

FIG. 12 is a partial cross sectional view illustrating a barrier layerformed on the contact hole for explaining the modified example of thepresent invention.

DETAILED DESCRIPTION OF THE INVENTION

With reference to the drawings, a semiconductor device obtained by thepresent invention will be described below.

FIG. 3 is a cross sectional view partially illustrating substantialparts of a configuration of the semiconductor device according to anembodiment of the present invention.

The semiconductor device 100 is a semiconductor device having an Nchannel insulated gate field effect transistor (N channel MOS)structure. Provided on a high-concentration N-type diffusion layer 19 ofthis semiconductor device 100 is a contact plug, of which an examplestructure is illustrated in FIG. 3.

As shown in FIG. 3, the high-concentration N-type diffusion layer 19 isprovided in a P-type well 8 provided in the semiconductor siliconsubstrate 1.

As is not specifically illustrated, but as is the case with FIGS. 2A and2B explained above, a P-type high-concentration well layer may beprovided on a semiconductor silicon substrate surface of the P-type well8.

The high-concentration N-type diffusion layer 19 corresponds to asource/drain structure of the semiconductor device 100. Provided withthis source/drain structure, a gate electrode structure (not shown) andthe like the semiconductor device serves as N channel MOS.

Further, the semiconductor device 100 has a contact plug 7 as shown inFIG. 3.

This contact plug 7 is generally composed of at least one of tungsten,polysilicon containing impurities, and so on.

The above-mentioned impurities include, for example, phosphorus andboron.

The contact plug 7 is provided on an interlayer insulating film 2 andthe semiconductor silicon substrate 1 via a barrier layer 6.

The interlayer insulating film 2 is composed of, for example, SiO₂.

Further, the barrier layer 6 is composed of, for example, at least oneof TiN, TaN and so on.

For ease of handling, the barrier layer 6 is preferably composed of TiN.

Besides, the barrier layer 6 is provided in contact with a portioncalled “contact hole” which is defined by the interlayer insulating film2 and the semiconductor silicon substrate 1.

In the present invention, the depth of the contact hole preferablyranges from 400 to 1000 nm for ease of handling.

In addition, the diameter of the bottom of the contact hole, i.e. aportion of the contact hole corresponding to the surface of thesemiconductor silicon substrate 1, preferably ranges from 50 to 260 nm.The diameter of the upper portion of the contact hole, i.e. a portion ofthe contact hole almost in the same plane as the upper surface of theinterlayer insulating film 2 preferably ranges from 100 to 300 nm.

Further, in the semiconductor silicon substrate 1 an indium-containinglayer 12 is formed in the high-concentration N-type diffusion layer 19.The indium-containing layer 12 is a layer formed at the surface of thesemiconductor silicon substrate 1.

In order to reduce the resistance of the contact plug 7, theindium-containing layer 12 has a depth of 25 nm or more, or preferably50 nm, from the surface of the semiconductor silicon substrate 1.

The concentration of indium contained in the indium-containing layer 12preferably ranges from 5.0×10¹⁸ to 5.0×10¹⁹/cm³, or more preferably from5.0×10¹⁸ to 1.0×10¹⁹/cm³.

Further, formed at a boundary region between the indium-containing layer12 and the barrier layer 6 is a metal silicide compound layer 501.

Such a metal silicide compound layer 501 is composed of at least one ofTiSi₂, CoSi₂, TaSi₂, PtSi₂, NiSi₂ and the like.

The metal silicide compound layer 501 is preferably of at least oneselected from the group consisting of TiSi₂, CoSi₂ and NiSi₂, or morepreferably of TiSi₂.

EXAMPLE 1

Next description is made in detail about the manufacturing method of thepresent invention based on the following example with reference to thedrawings. Here, the present invention is not limited to the embodimentdescribed in the following example.

The manufacturing method of the present invention includes a step (1) offorming a high-concentration N-type diffusion layer 19 at a surface ofthe semiconductor silicon substrate 1 as illustrated in FIG. 4.

The semiconductor silicon substrate 1 contained B ions at aconcentration ranging from 10¹⁶/cm³ to 10¹⁸/cm³ and the P-type well 8was formed therein.

A predetermined position of the P-type well 8 was implanted once with Asions at an energy of 10 keV and an implantation amount of 2.8×10¹⁴ cm²from the vertical direction relative to the semiconductor siliconsubstrate 1.

This was followed by implanting once P ions at an energy of 18 keV andan implantation amount of 3.0×10¹³ cm² from the vertical directionrelative to the semiconductor silicon substrate 1. Then, As ions werefurther implanted at an energy of 35 keV and an implantation amount of4.0×10¹⁵ cm² from the vertical direction relative to the semiconductorsilicon substrate 1.

Further, these ions were diffused at temperatures ranging from 950 to1000° C. thereby to form the high-concentration N-type diffusion layer19.

The high-concentration N-type diffusion layer 19 at the point of iondiffusion had a depth ranging from 100 to 150 nm from the surface of thesemiconductor silicon substrate 1.

The high-concentration N-type diffusion layer 19 corresponds to asource/drain structure of the N channel MOS semiconductor deviceobtained by the manufacturing method of the present invention. Providedwith this source/drain structure, a gate electrode structure (not shown)and the like, the semiconductor device obtained by the manufacturingmethod of the present invention serves as N channel MOS.

Besides, the manufacturing method of the present invention includes astep (2) of forming an interlayer insulating film 2 on the semiconductorsilicon substrate 1 provided with the high-concentration N-typediffusion layer 19, as illustrated in FIG. 5.

The interlayer insulating film 2 is formed by a well known method andfor example, may be formed by using SiO₂, BPSG (Boron PhosphorousSilicate Glass) or the like.

The manufacturing method of the present invention includes a step (3) ofperforming etching on a predetermined portion of the interlayerinsulating film 2 to form a contact hole which reaches thehigh-concentration N-type diffusion layer 19, as illustrated in FIG. 6.

A photoresist layer (not shown) was formed at a predetermined portion onthe interlayer insulating film 2 and this photoresist layer was used asa mask to perform well-known etching processing such as dry etchingthereby to form the contact hole 3 illustrated in FIG. 6.

The thus-formed contact hole had a depth ranging from 550 to 750 nm.

In addition, the diameter of the bottom of the contact hole 3, i.e. aportion of the contact hole 3 corresponding to a surface of thesemiconductor silicon substrate 1, ranged from 60 to 160 nm. Thediameter of the upper portion of the contact hole, i.e. a portion of thecontact hole almost in the same plane as the upper surface of theinterlayer insulating film 2 ranged from 110 to 190 nm.

Further, the manufacturing method of the present invention includes astep (4) of implanting the surface of the high-concentration N-typediffusion layer via the contact hole with indium ions at an energyranging from 30 to 120 keV and an implantation amount ranging from1.0×10¹³ to 5.0×10¹⁴/cm² to form an indium-containing layer 12 on thebottom of the contact hole.

This processing of indium ion implantation makes the indium-containinglayer 12 grow over the high-concentration N-type diffusion layer 19 andthereby it becomes possible to reduce the resistance of the contactplug.

Here, prior to indium ion implantation, phosphorus ions were implantedto the surface of the high-concentration N-type diffusion layer via thecontact hole at an energy ranging from 5 to 10 keV and an implantationamount ranging from 1.0×10¹³ to 3.0×10¹³/cm².

After indium ion implantation, the semiconductor silicon substrate 1 washeated for annealing with use of a lump light source in a nitrogenatmosphere at the temperature of 700° C. for 60 seconds thereby to formthe indium-containing layer 12.

Further, the manufacturing method of the present invention includes astep (5) of forming a metal silicide layer on the indium-containinglayer 12 formed at the bottom of the contact hole 3 and a step (6) offorming a barrier layer 6 on the upper surface of the interlayerinsulating film 2 and the inner surface of the contact hole 3 other thanthe bottom of the contact hole.

TiCl₄ gas at a flow rate of 12 cm³/m was made to react with H₂ gas at aflow rate of 4000 cm³/m and Ar gas at a flow rate of 1600 cm³/m at atemperature of 650° C., and as a result of CVD, the metal silicide layer501 was formed of TiSi₂ with a film thickness of 10 nm, which isillustrated in FIG. 8.

Then, TiCl₄ gas at a flow rate of 63 cm³/m was made to react with NH₃gas at a flow rate of 240 cm³/m and N₂ gas at a flow rate of 5500 cm³/mat a temperature of 650° C., and as a result of CVD, a barrier layer 6of TiN with a film thickness of 12.5 nm was deposited on the metalsilicide layer 501 of TiSi₂.

In this example, the semiconductor device was manufactured having themetal silicide layer 501 of TiSi₂ as described above. However, thesemiconductor device can be manufactured to have a metal silicide layerof CoSi₂, which method is described below.

First, on the inner surface of the contact hole 3 and the upper surfaceof the interlayer insulating film 2 shown in FIG. 7, a sputtering methodor the like is used to deposit a cobalt layer 401 which is illustratedin FIG. 9. There is no particular limitation in the sputtering methodand it can be performed by any well-known technique.

This is followed by heating treatment and whereby the cobalt layer 401at the bottom of the contact hole 3 is made react with the silicon inthe semiconductor silicon substrate to deposit a metal silicide layer502 of CoSi₂.

After removing the cobalt layer 401 by any well-known method such asetching as illustrated in FIG. 11, a barrier layer 6 of TiN can beformed on the metal silicide layer 502 of CoSi₂ by the same method asdescribed above, which is shown in FIG. 12.

Next, the manufacturing method of the present invention includes a step(7) of forming a contact plug 7 in the contact hole as illustrated inFIG. 3.

WF₆ gas at a flow rate of 340 cm³/m was made to react with H₂ gas at aflow rate of 2200 cm³/m, Ar gas at a flow rate of 4000 cm³/m and N₂ gasat a flow rate of 200 cm³/m at a temperature of 450° C. and as a resultof CVD, the contact plug 7 of tungsten was formed.

After deposition of the contact plug, etching, CMP or other processingcan be used to fix the shape of the contact plug 7.

After fixing the shape of the contact plug 7, the semiconductor devicecan be completed following a well-known method.

Thus, the manufacturing method including the above-described steps (1)through (7) makes it possible to obtain a semiconductor device.

The resistance value of the contact plug obtained in the above-describedmanufacturing method ranged from 360 to 420Ω while the resistance valueof the contact plug 7 when the indium-containing layer 12 was notprovided ranged from 580 to 640Ω.

In addition, in the above-described example 1, the acceleration energyof the indium ions was set at 60 keV, and the implantation amounts ofthe indium ions were compared between 1.0×10¹³/cm² and 8.0×10¹⁴/cm².Then, the resistance values of the contact plugs obtained in these werealmost the same.

The present invention is not limited to the above described embodiments,and various variations and modifications may be possible withoutdeparting from the scope of the present invention.

This application is based on the Japanese Patent application No.2005-136726 filed on May 9, 2005, entire content of which is expresslyincorporated by reference herein.

1-9. (canceled)
 10. A semiconductor device comprising: a semiconductorsilicon substrate; a high-concentration N-type diffusion layer providedon a surface of said semiconductor silicon substrate; anindium-containing layer provided in said high-concentration N-typediffusion layer; an interlayer insulating film provided at apredetermined position on said semiconductor silicon substrate; abarrier layer provided in contact with an inner surface of a contacthole defined by the surface of said semiconductor silicon substrate andsaid interlayer insulating film and with said interlayer insulatingfilm; a contact plug provided in contact with said barrier layer; and ametal silicide layer provided at a boundary region between saidindium-containing layer and said barrier layer, wherein indiumconcentration of said indium-containing layer ranges from 5.0×10¹⁸/cm³to 5.0×10¹⁹/cm³.
 11. The semiconductor device according to claim 10,comprising an N channel insulated gate field effect transistorstructure.
 12. The semiconductor device according to claim 10,comprising an N channel insulated gate field effect transistorstructure.
 13. The semiconductor device according to claim 10, whereinthe metal silicide layer has a thickness of about 10 nm, theindium-containing layer has a depth of 25 nm or more from the surface ofthe semiconductor substrate, and the high-concentration N-type diffusionlayer has a depth of 100 to 150 nm from the surface of the semiconductorsubstrate.
 14. A semiconductor device comprising: a semiconductorsilicon substrate; a high-concentration N-type diffusion layer providedon a surface of said semiconductor silicon substrate; anindium-containing layer provided in said high-concentration N-typediffusion layer; an interlayer insulating film provided at apredetermined position on said semiconductor silicon substrate; abarrier layer provided in contact with an inner surface of a contacthole defined by the surface of said semiconductor silicon substrate andsaid interlayer insulating film and with said interlayer insulatingfilm; a contact plug provided in contact with said barrier layer; and ametal silicide layer provided at a boundary region between saidindium-containing layer and said barrier layer, wherein the metalsilicide layer has a thickness of about 10 nm, the indium-containinglayer has a depth of 25 nm or more from the surface of the semiconductorsubstrate, and the high-concentration N-type diffusion layer has a depthof 100 to 150 nm from the surface of the semiconductor substrate. 15.The semiconductor device according to claim 14, comprising an N channelinsulated gate field effect transistor structure.
 16. The semiconductordevice according to claim 10, comprising an N channel insulated gatefield effect transistor structure.
 17. A semiconductor device having anN-channel insulated gate transistor, the transistor comprising N-typesource and N-type drain regions selectively formed in P-type region todefine a channel region therebetween, an insulated gate structurecovering the channel region, and source and drain electrodes formed incontact respectively with the N-type source and N-type drain regions, atleast one of the N-type source and N-type drain regions including afirst portion which represents the N-type and which contains indium anda second portion which represents the N-type and which containssubstantially no indium, the first portion being surrounded by thesecond portion and in contact with a corresponding one of the source anddrain electrodes.
 18. The device as claimed in claim 17, wherein each ofthe first and second portions is doped with N-type impurities at a highconcentration to represent the N-type.
 19. The device as claimed inclaim 17, wherein the first portion contains indium at a concentrationof 5.0×10¹⁸/cm³ to 5.0×10¹⁹/cm³.
 20. The device as claimed in claim 17,further comprising an insulating layer covering the transistor and acontact hole selectively formed in the insulating layer to expose a partof the first portion, the corresponding one of the source and drainelectrodes including a metal silicide layer formed in contact with thepart of the first portion and a contact plug filling the contact hole incontact with the metal silicide layer.
 21. The device as claimed inclaim 20, wherein the contact plug includes a conductive layer and abarrier metal layer sandwiched between the conductive layer and themetal silicide layer.
 22. The device as claimed in claim 21, wherein thefirst portion contains indium at a concentration of 5.0×10¹⁸/cm³ to5.0×10¹⁹/cm³.